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325 lines
12 KiB
Markdown
Executable File
325 lines
12 KiB
Markdown
Executable File
# Dynarmic Design Documentation
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Dynarmic is a dynamic recompiler for the ARMv6K architecture. Future plans for dynarmic include
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support for other versions of the ARM architecture, having a interpreter mode, and adding support
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for other architectures.
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Users of this library interact with it primarily through the interface provided in
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[`src/dynarmic/interface`](../src/dynarmic/interface). Users specify how dynarmic's CPU core interacts with
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the rest of their system providing an implementation of the relevant `UserCallbacks` interface.
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Users setup the CPU state using member functions of `Jit`, then call `Jit::Execute` to start CPU
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execution. The callbacks defined on `UserCallbacks` may be called from dynamically generated code,
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so users of the library should not depend on the stack being in a walkable state for unwinding.
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* A32: [`Jit`](../src/dynarmic/interface/A32/a32.h), [`UserCallbacks`](../src/dynarmic/interface/A32/config.h)
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* A64: [`Jit`](../src/dynarmic/interface/A64/a64.h), [`UserCallbacks`](../src/dynarmic/interface/A64/config.h)
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Dynarmic reads instructions from memory by calling `UserCallbacks::MemoryReadCode`. These
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instructions then pass through several stages:
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1. Decoding (Identifying what type of instruction it is and breaking it up into fields)
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2. Translation (Generation of high-level IR from the instruction)
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3. Optimization (Eliminiation of redundant microinstructions, other speed improvements)
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4. Emission (Generation of host-executable code into memory)
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5. Execution (Host CPU jumps to the start of emitted code and runs it)
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Using the A32 frontend with the x64 backend as an example:
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* Decoding is done by [double dispatch](https://en.wikipedia.org/wiki/Visitor_pattern) in
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../src/dynarmic/frontend/A32/decoder/).
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* Translation is done by the visitors in [`src/dynarmic/frontend/A32/translate/translate_{arm,thumb}.cpp`](../src/dynarmic/frontend/A32/translate/).
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The function [`Translate`](../src/dynarmic/frontend/A32/translate/translate.h) takes a starting memory location,
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some CPU state, and memory reader callback and returns a basic block of IR.
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* The IR can be found under [`src/frontend/ir/`](../src/dynarmic/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/dynarmic/ir/opt/).
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* Emission is done by `EmitX64` which can be found in [`src/dynarmic/backend/x64/emit_x64.{h,cpp}`](../src/dynarmic/backend/x64/).
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* Execution is performed by calling `BlockOfCode::RunCode` in [`src/dynarmic/backend/x64/block_of_code.{h,cpp}`](../src/dynarmic/backend/x64/).
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## Decoder
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The decoder is a double dispatch decoder. Each instruction is represented by a line in the relevant
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instruction table. Here is an example line from [`arm.h`](../src/dynarmic/frontend/A32/decoder/arm.h):
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv")
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(Details on this instruction can be found in section A8.8.1 of the ARMv7-A manual. This is encoding A1.)
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The first argument to INST is the member function to call on the visitor. The second argument is a user-readable
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instruction name. The third argument is a bit-representation of the instruction.
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### Instruction Bit-Representation
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Each character in the bitstring represents a bit. A `0` means that that bitposition **must** contain a zero. A `1`
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means that that bitposition **must** contain a one. A `-` means we don't care about the value at that bitposition.
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A string of the same character represents a field. In the above example, the first four bits `cccc` represent the
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four-bit-long cond field of the ARM Add with Carry (immediate) instruction.
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The visitor would have to have a function named `arm_ADC_imm` with 6 arguments, one for each field (`cccc`, `S`,
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`nnnn`, `dddd`, `rrrr`, `vvvvvvvv`). If there is a mismatch of field number with argument number, a compile-time
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error results.
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## Translator
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The translator is a visitor that uses the decoder to decode instructions. The translator generates IR code with the
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help of the [`IREmitter` class](../src/dynarmic/ir/ir_emitter.h). An example of a translation function follows:
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bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// ADC{S}<c> <Rd>, <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.GetCFlag());
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if (d == Reg::PC) {
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ASSERT(!S);
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ir.ALUWritePC(result.result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, result.result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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}
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return true;
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}
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where `ir` is an instance of the `IRBuilder` class. Each member function of the `IRBuilder` class constructs
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an IR microinstruction.
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## Intermediate Representation
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Dynarmic uses an ordered SSA intermediate representation. It is very vaguely similar to those found in other
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similar projects like redream, nucleus, and xenia. Major differences are: (1) the abundance of context
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microinstructions whereas those projects generally only have two (`load_context`/`store_context`), (2) the
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explicit handling of flags as their own values, and (3) very different basic block edge handling.
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The intention of the context microinstructions and explicit flag handling is to allow for future optimizations. The
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differences in the way edges are handled are a quirk of the current implementation and dynarmic will likely add a
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function analyser in the medium-term future.
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Dynarmic's intermediate representation is typed. Each microinstruction may take zero or more arguments and may
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return zero or more arguments. A subset of the microinstructions available is documented below.
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A complete list of microinstructions can be found in [src/dynarmic/ir/opcodes.inc](../src/dynarmic/ir/opcodes.inc).
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The below lists some commonly used microinstructions.
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### Immediate: Imm{U1,U8,U32,RegRef}
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<u1> ImmU1(u1 value)
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<u8> ImmU8(u8 value)
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<u32> ImmU32(u32 value)
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<RegRef> ImmRegRef(Arm::Reg gpr)
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These instructions take a `bool`, `u8` or `u32` value and wraps it up in an IR node so that they can be used
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by the IR.
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### Context: {Get,Set}Register
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<u32> GetRegister(<RegRef> reg)
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<void> SetRegister(<RegRef> reg, <u32> value)
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Gets and sets `JitState::Reg[reg]`. Note that `SetRegister(Arm::Reg::R15, _)` is disallowed by IRBuilder.
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Use `{ALU,BX}WritePC` instead.
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Note that sequences like `SetRegister(R4, _)` followed by `GetRegister(R4)` are
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optimized away.
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### Context: {Get,Set}{N,Z,C,V}Flag
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<u1> GetNFlag()
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<void> SetNFlag(<u1> value)
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<u1> GetZFlag()
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<void> SetZFlag(<u1> value)
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<u1> GetCFlag()
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<void> SetCFlag(<u1> value)
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<u1> GetVFlag()
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<void> SetVFlag(<u1> value)
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Gets and sets bits in `JitState::Cpsr`. Similarly to registers redundant get/sets are optimized away.
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### Context: BXWritePC
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<void> BXWritePC(<u32> value)
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This should probably be the last instruction in a translation block unless you're doing something fancy.
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This microinstruction sets R15 and CPSR.T as appropriate.
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### Callback: CallSupervisor
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<void> CallSupervisor(<u32> svc_imm32)
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This should probably be the last instruction in a translation block unless you're doing something fancy.
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### Calculation: LastSignificant{Half,Byte}
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<u16> LeastSignificantHalf(<u32> value)
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<u8> LeastSignificantByte(<u32> value)
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Extract a u16 and u8 respectively from a u32.
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### Calculation: MostSignificantBit, IsZero
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<u1> MostSignificantBit(<u32> value)
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<u1> IsZero(<u32> value)
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These are used to implement ARM flags N and Z. These can often be optimized away by the backend into a host flag read.
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### Calculation: LogicalShiftLeft
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(<u32> result, <u1> carry_out) LogicalShiftLeft(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = operand * (2 ** shift_amount)
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result = Bits<31,0>(x)
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carry_out = Bit<32>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SHL` does on x64).
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### Calculation: LogicalShiftRight
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(<u32> result, <u1> carry_out) LogicalShiftLeft(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = ZeroExtend(operand, from_size: 32, to_size: shift_amount+32)
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result = Bits<shift_amount+31,shift_amount>(x)
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carry_out = Bit<shift_amount-1>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SHR` does on x64).
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### Calculation: ArithmeticShiftRight
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(<u32> result, <u1> carry_out) ArithmeticShiftRight(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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x = SignExtend(operand, from_size: 32, to_size: shift_amount+32)
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result = Bits<shift_amount+31,shift_amount>(x)
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carry_out = Bit<shift_amount-1>(x)
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return (result, carry_out)
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This follows ARM semantics. Note `shift_amount` is not masked to 5 bits (like `SAR` does on x64).
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### Calcuation: RotateRight
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(<u32> result, <u1> carry_out) RotateRight(<u32> operand, <u8> shift_amount, <u1> carry_in)
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Pseudocode:
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if shift_amount == 0:
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return (operand, carry_in)
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shift_amount %= 32
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result = (operand << shift_amount) | (operand >> (32 - shift_amount))
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carry_out = Bit<31>(result)
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return (result, carry_out)
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### Calculation: AddWithCarry
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(<u32> result, <u1> carry_out, <u1> overflow) AddWithCarry(<u32> a, <u32> b, <u1> carry_in)
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a + b + carry_in
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### Calculation: SubWithCarry
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(<u32> result, <u1> carry_out, <u1> overflow) SubWithCarry(<u32> a, <u32> b, <u1> carry_in)
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This has equivalent semantics to `AddWithCarry(a, Not(b), carry_in)`.
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a - b - !carry_in
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### Calculation: And
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<u32> And(<u32> a, <u32> b)
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### Calculation: Eor
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<u32> Eor(<u32> a, <u32> b)
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Exclusive OR (i.e.: XOR)
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### Calculation: Or
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<u32> Or(<u32> a, <u32> b)
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### Calculation: Not
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<u32> Not(<u32> value)
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### Callback: {Read,Write}Memory{8,16,32,64}
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<u8> ReadMemory8(<u32> vaddr)
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<u8> ReadMemory16(<u32> vaddr)
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<u8> ReadMemory32(<u32> vaddr)
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<u8> ReadMemory64(<u32> vaddr)
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<void> WriteMemory8(<u32> vaddr, <u8> value_to_store)
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<void> WriteMemory16(<u32> vaddr, <u16> value_to_store)
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<void> WriteMemory32(<u32> vaddr, <u32> value_to_store)
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<void> WriteMemory64(<u32> vaddr, <u64> value_to_store)
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Memory access.
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### Terminal: Interpret
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SetTerm(IR::Term::Interpret{next})
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This terminal instruction calls the interpreter, starting at `next`.
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The interpreter must interpret exactly one instruction.
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### Terminal: ReturnToDispatch
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SetTerm(IR::Term::ReturnToDispatch{})
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This terminal instruction returns control to the dispatcher.
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The dispatcher will use the value in R15 to determine what comes next.
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### Terminal: LinkBlock
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SetTerm(IR::Term::LinkBlock{next})
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This terminal instruction jumps to the basic block described by `next` if we have enough
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cycles remaining. If we do not have enough cycles remaining, we return to the
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dispatcher, which will return control to the host.
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### Terminal: PopRSBHint
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SetTerm(IR::Term::PopRSBHint{})
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This terminal instruction checks the top of the Return Stack Buffer against R15.
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If RSB lookup fails, control is returned to the dispatcher.
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This is an optimization for faster function calls. A backend that doesn't support
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this optimization or doesn't have a RSB may choose to implement this exactly as
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ReturnToDispatch.
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### Terminal: If
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SetTerm(IR::Term::If{cond, term_then, term_else})
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This terminal instruction conditionally executes one terminal or another depending
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on the run-time state of the ARM flags.
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