mirror of
https://github.com/pineappleEA/pineapple-src.git
synced 2024-11-25 18:28:25 -05:00
early-access version 1952
This commit is contained in:
parent
0f29a1f4ef
commit
92d13687fe
@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 1951.
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This is the source code for early-access 1952.
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## Legal Notice
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@ -5,10 +5,8 @@
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/service/nvdrv/devices/nvdisp_disp0.h"
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#include "core/hle/service/nvdrv/devices/nvmap.h"
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#include "core/perf_stats.h"
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#include "video_core/gpu.h"
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#include "video_core/renderer_base.h"
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@ -41,7 +39,7 @@ void nvdisp_disp0::OnClose(DeviceFD fd) {}
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void nvdisp_disp0::flip(u32 buffer_handle, u32 offset, u32 format, u32 width, u32 height,
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u32 stride, NVFlinger::BufferQueue::BufferTransformFlags transform,
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const Common::Rectangle<int>& crop_rect) {
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const Common::Rectangle<int>& crop_rect, const MultiFence& fences) {
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VAddr addr = nvmap_dev->GetObjectAddress(buffer_handle);
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LOG_TRACE(Service,
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"Drawing from address {:X} offset {:08X} Width {} Height {} Stride {} Format {}",
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@ -52,10 +50,7 @@ void nvdisp_disp0::flip(u32 buffer_handle, u32 offset, u32 format, u32 width, u3
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addr, offset, width, height, stride, static_cast<PixelFormat>(format),
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transform, crop_rect};
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system.GetPerfStats().EndSystemFrame();
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system.GPU().SwapBuffers(&framebuffer);
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system.SpeedLimiter().DoSpeedLimiting(system.CoreTiming().GetGlobalTimeUs());
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system.GetPerfStats().BeginSystemFrame();
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system.GPU().QueueFrame(&framebuffer, fences);
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}
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} // namespace Service::Nvidia::Devices
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@ -33,7 +33,7 @@ public:
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/// Performs a screen flip, drawing the buffer pointed to by the handle.
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void flip(u32 buffer_handle, u32 offset, u32 format, u32 width, u32 height, u32 stride,
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NVFlinger::BufferQueue::BufferTransformFlags transform,
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const Common::Rectangle<int>& crop_rect);
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const Common::Rectangle<int>& crop_rect, const MultiFence& fence);
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private:
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std::shared_ptr<nvmap> nvmap_dev;
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@ -88,6 +88,10 @@ const IGBPBuffer& BufferQueue::RequestBuffer(u32 slot) const {
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return buffers[slot].igbp_buffer;
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}
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const BufferQueue::Buffer& BufferQueue::AccessBuffer(u32 slot) const {
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return buffers[slot];
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}
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void BufferQueue::QueueBuffer(u32 slot, BufferTransformFlags transform,
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const Common::Rectangle<int>& crop_rect, u32 swap_interval,
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Service::Nvidia::MultiFence& multi_fence) {
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@ -107,6 +107,7 @@ public:
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void Connect();
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void Disconnect();
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u32 Query(QueryType type);
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const Buffer& AccessBuffer(u32 slot) const;
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u32 GetId() const {
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return id;
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@ -274,8 +274,6 @@ void NVFlinger::Compose() {
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continue;
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}
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const auto& igbp_buffer = buffer->get().igbp_buffer;
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if (!system.IsPoweredOn()) {
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return; // We are likely shutting down
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}
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@ -289,21 +287,29 @@ void NVFlinger::Compose() {
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}
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guard->lock();
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system.GetPerfStats().EndSystemFrame();
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MicroProfileFlip();
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system.SpeedLimiter().DoSpeedLimiting(system.CoreTiming().GetGlobalTimeUs());
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system.GetPerfStats().BeginSystemFrame();
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swap_interval = buffer->get().swap_interval;
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buffer_queue.ReleaseBuffer(buffer->get().slot);
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}
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}
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void NVFlinger::PrequeueFrame(u32 buffer_queue_id, u32 slot) {
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auto& buffer_queue = *FindBufferQueue(buffer_queue_id);
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const auto& buffer = buffer_queue.AccessBuffer(slot);
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const auto& igbp_buffer = buffer.igbp_buffer;
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// Now send the buffer to the GPU for drawing.
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// TODO(Subv): Support more than just disp0. The display device selection is probably based
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// on which display we're drawing (Default, Internal, External, etc)
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auto nvdisp = nvdrv->GetDevice<Nvidia::Devices::nvdisp_disp0>("/dev/nvdisp_disp0");
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ASSERT(nvdisp);
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nvdisp->flip(igbp_buffer.gpu_buffer_id, igbp_buffer.offset, igbp_buffer.format,
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igbp_buffer.width, igbp_buffer.height, igbp_buffer.stride,
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buffer->get().transform, buffer->get().crop_rect);
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swap_interval = buffer->get().swap_interval;
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buffer_queue.ReleaseBuffer(buffer->get().slot);
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}
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igbp_buffer.width, igbp_buffer.height, igbp_buffer.stride, buffer.transform,
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buffer.crop_rect, buffer.multi_fence);
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}
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s64 NVFlinger::GetNextTicks() const {
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@ -77,6 +77,8 @@ public:
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/// Obtains a buffer queue identified by the ID.
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[[nodiscard]] BufferQueue* FindBufferQueue(u32 id);
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void PrequeueFrame(u32 buffer_queue_id, u32 slot);
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/// Performs a composition request to the emulated nvidia GPU and triggers the vsync events when
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/// finished.
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void Compose();
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@ -592,6 +592,7 @@ private:
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buffer_queue.QueueBuffer(request.data.slot, request.data.transform,
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request.data.GetCropRect(), request.data.swap_interval,
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request.data.multi_fence);
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nv_flinger.PrequeueFrame(id, request.data.slot);
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IGBPQueueBufferResponseParcel response{1280, 720};
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ctx.WriteBuffer(response.Serialize());
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@ -114,10 +114,17 @@ void GPU::WaitFence(u32 syncpoint_id, u32 value) {
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});
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}
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void GPU::IncrementSyncPointGuest(const u32 syncpoint_id) {
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std::lock_guard lock{pre_sync_mutex};
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auto& syncpoint = pre_syncpoints.at(syncpoint_id);
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syncpoint++;
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ProcessFrameRequests(syncpoint_id, syncpoint);
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}
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void GPU::IncrementSyncPoint(const u32 syncpoint_id) {
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std::lock_guard lock{sync_mutex};
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auto& syncpoint = syncpoints.at(syncpoint_id);
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syncpoint++;
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std::lock_guard lock{sync_mutex};
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sync_cv.notify_all();
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auto& interrupt = syncpt_interrupts.at(syncpoint_id);
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if (!interrupt.empty()) {
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@ -162,25 +169,121 @@ bool GPU::CancelSyncptInterrupt(const u32 syncpoint_id, const u32 value) {
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return true;
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}
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void GPU::WaitOnWorkRequest(u64 fence) {
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std::unique_lock lck{work_request_mutex};
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request_cv.wait(lck,
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[&] { return fence >= current_request_fence.load(std::memory_order_relaxed); });
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}
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u64 GPU::RequestFlush(VAddr addr, std::size_t size) {
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std::unique_lock lck{flush_request_mutex};
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const u64 fence = ++last_flush_fence;
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flush_requests.emplace_back(fence, addr, size);
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std::unique_lock lck{work_request_mutex};
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const u64 fence = ++last_request_fence;
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work_requests.emplace_back(fence, addr, size);
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return fence;
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}
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u64 GPU::RequestQueueFrame(u64 id) {
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std::unique_lock lck{work_request_mutex};
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const u64 fence = ++last_request_fence;
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work_requests.emplace_back(fence, id);
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return fence;
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}
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void GPU::TickWork() {
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std::unique_lock lck{flush_request_mutex};
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while (!flush_requests.empty()) {
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auto& request = flush_requests.front();
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std::unique_lock lck{work_request_mutex};
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while (!work_requests.empty()) {
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auto request = work_requests.front();
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const u64 fence = request.fence;
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const VAddr addr = request.addr;
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const std::size_t size = request.size;
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flush_requests.pop_front();
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flush_request_mutex.unlock();
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rasterizer->FlushRegion(addr, size);
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current_flush_fence.store(fence);
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flush_request_mutex.lock();
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work_requests.pop_front();
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work_request_mutex.unlock();
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switch (request.type) {
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case RequestType::Flush: {
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rasterizer->FlushRegion(request.flush.addr, request.flush.size);
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break;
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}
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case RequestType::QueueFrame: {
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Tegra::FramebufferConfig frame_info;
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{
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std::unique_lock<std::mutex> lock(frame_requests_mutex);
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const u64 searching_id = request.queue_frame.id;
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auto it = std::find_if(
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frame_queue_items.begin(), frame_queue_items.end(),
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[searching_id](const FrameQueue& item) { return item.id == searching_id; });
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ASSERT(it != frame_queue_items.end());
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frame_info = it->frame_info;
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frame_queue_items.erase(it);
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}
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renderer->SwapBuffers(&frame_info);
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break;
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}
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default: {
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LOG_ERROR(HW_GPU, "Unknown work request type={}", request.type);
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}
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}
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current_request_fence.store(fence, std::memory_order_release);
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work_request_mutex.lock();
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request_cv.notify_all();
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}
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}
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void GPU::QueueFrame(const Tegra::FramebufferConfig* framebuffer,
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const Service::Nvidia::MultiFence& fences) {
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std::unique_lock<std::mutex> lock(frame_requests_mutex);
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if (fences.num_fences == 0) {
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u64 new_queue_id = frame_queue_ids++;
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FrameQueue item{
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.frame_info = *framebuffer,
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.id = new_queue_id,
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};
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frame_queue_items.push_back(item);
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RequestQueueFrame(new_queue_id);
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return;
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}
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u64 new_id = frame_request_ids++;
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FrameRequest request{
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.frame_info = *framebuffer,
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.count = 0,
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.id = new_id,
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};
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std::unique_lock lck{pre_sync_mutex};
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for (size_t i = 0; i < fences.num_fences; i++) {
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auto& fence = fences.fences[i];
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if (pre_syncpoints[fence.id].load(std::memory_order_relaxed) < fence.value) {
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const FrameTrigger trigger{
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.id = new_id,
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.sync_point_value = fence.value,
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};
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frame_triggers[fence.id].push_back(trigger);
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++request.count;
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}
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}
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if (request.count == 0) {
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lck.unlock();
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gpu_thread.SwapBuffers(framebuffer);
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return;
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}
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frame_requests.emplace(new_id, request);
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}
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void GPU::ProcessFrameRequests(u32 syncpoint_id, u32 new_value) {
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auto& list = frame_triggers[syncpoint_id];
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if (list.empty()) {
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return;
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}
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auto it = list.begin();
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while (it != list.end()) {
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if (it->sync_point_value <= new_value) {
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auto obj = frame_requests.find(it->id);
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--obj->second.count;
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if (obj->second.count == 0) {
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rasterizer->FlushCommands();
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renderer->SwapBuffers(&obj->second.frame_info);
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frame_requests.erase(obj);
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}
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it = list.erase(it);
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continue;
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}
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++it;
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}
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}
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@ -399,7 +502,7 @@ void GPU::ProcessFenceActionMethod() {
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WaitFence(regs.fence_action.syncpoint_id, regs.fence_value);
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break;
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case FenceOperation::Increment:
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IncrementSyncPoint(regs.fence_action.syncpoint_id);
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rasterizer->SignalSyncPoint(regs.fence_action.syncpoint_id);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented operation {}", regs.fence_action.op.Value());
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@ -159,11 +159,16 @@ public:
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void OnCommandListEnd();
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/// Request a host GPU memory flush from the CPU.
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[[nodiscard]] u64 RequestFlush(VAddr addr, std::size_t size);
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u64 RequestFlush(VAddr addr, std::size_t size);
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void WaitOnWorkRequest(u64 fence);
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void QueueFrame(const Tegra::FramebufferConfig* framebuffer,
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const Service::Nvidia::MultiFence& fence);
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentFlushRequestFence() const {
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return current_flush_fence.load(std::memory_order_relaxed);
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[[nodiscard]] u64 CurrentWorkRequestFence() const {
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return current_request_fence.load(std::memory_order_relaxed);
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}
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/// Tick pending requests within the GPU.
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@ -225,6 +230,7 @@ public:
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/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame.
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void WaitFence(u32 syncpoint_id, u32 value);
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void IncrementSyncPointGuest(u32 syncpoint_id);
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void IncrementSyncPoint(u32 syncpoint_id);
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[[nodiscard]] u32 GetSyncpointValue(u32 syncpoint_id) const;
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@ -365,6 +371,34 @@ private:
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/// Determines where the method should be executed.
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[[nodiscard]] bool ExecuteMethodOnEngine(u32 method);
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struct FrameRequest {
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Tegra::FramebufferConfig frame_info;
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size_t count;
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u64 id;
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};
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struct FrameTrigger {
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u64 id;
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u32 sync_point_value;
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};
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struct FrameQueue {
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Tegra::FramebufferConfig frame_info;
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u64 id;
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};
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/// Request a frame release on the GPU thread
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u64 RequestQueueFrame(u64 id);
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void ProcessFrameRequests(u32 syncpoint_id, u32 new_value);
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std::mutex frame_requests_mutex;
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std::unordered_map<u32, std::list<FrameTrigger>> frame_triggers;
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std::unordered_map<u64, FrameRequest> frame_requests;
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std::list<FrameQueue> frame_queue_items;
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u64 frame_queue_ids{};
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u64 frame_request_ids{};
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protected:
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Core::System& system;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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@ -392,27 +426,50 @@ private:
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/// When true, we are about to shut down emulation session, so terminate outstanding tasks
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std::atomic_bool shutting_down{};
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> pre_syncpoints{};
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex pre_sync_mutex;
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std::mutex sync_mutex;
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std::mutex device_mutex;
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std::condition_variable sync_cv;
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struct FlushRequest {
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explicit FlushRequest(u64 fence_, VAddr addr_, std::size_t size_)
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: fence{fence_}, addr{addr_}, size{size_} {}
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u64 fence;
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VAddr addr;
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std::size_t size;
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enum class RequestType : u32 {
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Flush = 0,
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QueueFrame = 1,
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};
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std::list<FlushRequest> flush_requests;
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std::atomic<u64> current_flush_fence{};
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u64 last_flush_fence{};
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std::mutex flush_request_mutex;
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struct WorkRequest {
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explicit WorkRequest(u64 fence_, VAddr addr_, std::size_t size_)
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: fence{fence_}, type{RequestType::Flush} {
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flush.addr = addr_;
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flush.size = size_;
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}
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explicit WorkRequest(u64 fence_, u64 id) : fence{fence_}, type{RequestType::QueueFrame} {
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queue_frame.id = id;
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}
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u64 fence;
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union {
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struct {
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VAddr addr;
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std::size_t size;
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} flush;
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struct {
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u64 id;
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} queue_frame;
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};
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RequestType type;
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}; // namespace Tegra
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std::list<WorkRequest> work_requests;
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std::atomic<u64> current_request_fence{};
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u64 last_request_fence{};
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std::mutex work_request_mutex;
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std::condition_variable request_cv;
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const bool is_async;
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|
@ -105,7 +105,7 @@ void ThreadManager::FlushRegion(VAddr addr, u64 size) {
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auto& gpu = system.GPU();
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u64 fence = gpu.RequestFlush(addr, size);
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PushCommand(GPUTickCommand(), true);
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ASSERT(fence <= gpu.CurrentFlushRequestFence());
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ASSERT(fence <= gpu.CurrentWorkRequestFence());
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}
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void ThreadManager::InvalidateRegion(VAddr addr, u64 size) {
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|
@ -214,6 +214,8 @@ void RasterizerOpenGL::Clear() {
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||||
void RasterizerOpenGL::Draw(bool is_indexed, bool is_instanced) {
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MICROPROFILE_SCOPE(OpenGL_Drawing);
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SCOPE_EXIT({ gpu.TickWork(); });
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query_cache.UpdateCounters();
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SyncState();
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@ -269,8 +271,6 @@ void RasterizerOpenGL::Draw(bool is_indexed, bool is_instanced) {
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++num_queued_commands;
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has_written_global_memory |= pipeline->WritesGlobalMemory();
|
||||
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gpu.TickWork();
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||||
}
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||||
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void RasterizerOpenGL::DispatchCompute() {
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@ -421,6 +421,7 @@ void RasterizerOpenGL::SignalSemaphore(GPUVAddr addr, u32 value) {
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}
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|
||||
void RasterizerOpenGL::SignalSyncPoint(u32 value) {
|
||||
gpu.IncrementSyncPointGuest(value);
|
||||
if (!gpu.IsAsync()) {
|
||||
gpu.IncrementSyncPoint(value);
|
||||
return;
|
||||
|
@ -412,6 +412,7 @@ void RasterizerVulkan::SignalSemaphore(GPUVAddr addr, u32 value) {
|
||||
}
|
||||
|
||||
void RasterizerVulkan::SignalSyncPoint(u32 value) {
|
||||
gpu.IncrementSyncPointGuest(value);
|
||||
if (!gpu.IsAsync()) {
|
||||
gpu.IncrementSyncPoint(value);
|
||||
return;
|
||||
|
Loading…
Reference in New Issue
Block a user