mirror of
https://github.com/pineappleEA/pineapple-src.git
synced 2024-11-25 03:28:26 -05:00
early-access version 1546
This commit is contained in:
pineappleEA
parent
c7fcf99851
commit
0a011dc368
@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 1543.
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This is the source code for early-access 1546.
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## Legal Notice
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1
externals/dynarmic/src/CMakeLists.txt
vendored
1
externals/dynarmic/src/CMakeLists.txt
vendored
@ -163,6 +163,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
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frontend/A32/translate/impl/thumb32_load_byte.cpp
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frontend/A32/translate/impl/thumb32_load_halfword.cpp
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frontend/A32/translate/impl/thumb32_load_store_dual.cpp
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frontend/A32/translate/impl/thumb32_load_store_multiple.cpp
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frontend/A32/translate/impl/thumb32_load_word.cpp
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frontend/A32/translate/impl/thumb32_long_multiply.cpp
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@ -13,6 +13,7 @@
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#include "backend/x64/block_of_code.h"
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#include "backend/x64/perf_map.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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#ifdef _WIN32
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#include <windows.h>
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@ -43,8 +44,8 @@ const std::array<Xbyak::Reg64, 6> BlockOfCode::ABI_PARAMS = {BlockOfCode::ABI_PA
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namespace {
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constexpr size_t TOTAL_CODE_SIZE = 128 * 1024 * 1024;
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constexpr size_t FAR_CODE_OFFSET = 100 * 1024 * 1024;
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constexpr size_t TOTAL_CODE_SIZE = 256 * 1024 * 1024;
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constexpr size_t FAR_CODE_OFFSET = 200 * 1024 * 1024;
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constexpr size_t CONSTANT_POOL_SIZE = 2 * 1024 * 1024;
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class CustomXbyakAllocator : public Xbyak::Allocator {
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@ -364,7 +365,21 @@ bool BlockOfCode::HasBMI2() const {
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}
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bool BlockOfCode::HasFastBMI2() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tBMI2) && !DoesCpuSupport(Xbyak::util::Cpu::tAMD);
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if (DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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// BMI2 instructions such as pdep and pext have been very slow up until Zen 3.
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// Check for Zen 3 or newer by its family (0x19).
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// See also: https://en.wikichip.org/wiki/amd/cpuid
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if (DoesCpuSupport(Xbyak::util::Cpu::tAMD)) {
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std::array<u32, 4> data{};
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cpu_info.getCpuid(1, data.data());
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const u32 family_base = Common::Bits< 8, 11>(data[0]);
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const u32 family_extended = Common::Bits<20, 27>(data[0]);
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const u32 family = family_base + family_extended;
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return family >= 0x19;
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}
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return true;
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}
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return false;
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}
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bool BlockOfCode::HasFMA() const {
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@ -337,8 +337,12 @@ void EmitTwoOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
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ctx.reg_alloc.DefineValue(inst, result);
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}
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enum CheckInputNaN {
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Yes, No,
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};
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template<size_t fsize, template<typename> class Indexer, typename Function>
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void EmitThreeOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn, typename NaNHandler<fsize, Indexer, 3>::function_type nan_handler = NaNHandler<fsize, Indexer, 3>::GetDefault()) {
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void EmitThreeOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn, CheckInputNaN check_input_nan = CheckInputNaN::No, typename NaNHandler<fsize, Indexer, 3>::function_type nan_handler = NaNHandler<fsize, Indexer, 3>::GetDefault()) {
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static_assert(fsize == 32 || fsize == 64, "fsize must be either 32 or 64");
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -371,15 +375,31 @@ void EmitThreeOpVectorOperation(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
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const Xbyak::Xmm xmm_b = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm nan_mask = ctx.reg_alloc.ScratchXmm();
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code.movaps(nan_mask, xmm_b);
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code.movaps(result, xmm_a);
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FCODE(cmpunordp)(nan_mask, xmm_a);
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if (check_input_nan == CheckInputNaN::Yes) {
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if (code.HasAVX()) {
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FCODE(vcmpunordp)(nan_mask, xmm_a, xmm_b);
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} else {
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code.movaps(nan_mask, xmm_b);
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FCODE(cmpunordp)(nan_mask, xmm_a);
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}
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}
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, xmm_b);
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} else {
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fn(result, xmm_b);
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}
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FCODE(cmpunordp)(nan_mask, result);
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if (check_input_nan == CheckInputNaN::Yes) {
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FCODE(cmpunordp)(nan_mask, result);
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} else if (code.HasAVX()) {
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FCODE(vcmpunordp)(nan_mask, result, result);
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} else {
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code.movaps(nan_mask, result);
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FCODE(cmpunordp)(nan_mask, nan_mask);
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}
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HandleNaNs<fsize, 2>(code, ctx, fpcr_controlled, {result, xmm_a, xmm_b}, nan_mask, nan_handler);
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@ -951,7 +971,7 @@ static void EmitFPVectorMinMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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code.andnps(mask, eq);
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code.orps(result, mask);
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}
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});
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}, CheckInputNaN::Yes);
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}
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void EmitX64::EmitFPVectorMax32(EmitContext& ctx, IR::Inst* inst) {
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@ -13,17 +13,17 @@ INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100W1nnnniiiiii
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// Load/Store Dual, Load/Store Exclusive, Table Branch
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//INST(thumb32_STREX, "STREX", "111010000100--------------------")
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//INST(thumb32_LDREX, "LDREX", "111010000101--------------------")
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//INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000-110--------------------")
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//INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001-1-0--------------------")
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//INST(thumb32_LDRD_imm_1, "LDRD (lit)", "11101000-1111111----------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (lit)", "11101001-1-11111----------------")
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//INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000-111--------------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (imm)", "11101001-1-1--------------------")
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INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000U110nnnnttttssssiiiiiiii")
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INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001U1W0nnnnttttssssiiiiiiii")
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INST(thumb32_LDRD_lit_1, "LDRD (lit)", "11101000U1111111ttttssssiiiiiiii")
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INST(thumb32_LDRD_lit_2, "LDRD (lit)", "11101001U1W11111ttttssssiiiiiiii")
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INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000U111nnnnttttssssiiiiiiii")
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INST(thumb32_LDRD_imm_2, "LDRD (imm)", "11101001U1W1nnnnttttssssiiiiiiii")
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//INST(thumb32_STREXB, "STREXB", "111010001100------------0100----")
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//INST(thumb32_STREXH, "STREXH", "111010001100------------0101----")
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//INST(thumb32_STREXD, "STREXD", "111010001100------------0111----")
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//INST(thumb32_TBB, "TBB", "111010001101------------0000----")
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//INST(thumb32_TBH, "TBH", "111010001101------------0001----")
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INST(thumb32_TBB, "TBB", "111010001101nnnn111100000000mmmm")
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INST(thumb32_TBH, "TBH", "111010001101nnnn111100000001mmmm")
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//INST(thumb32_LDREXB, "LDREXB", "111010001101------------0100----")
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//INST(thumb32_LDREXH, "LDREXH", "111010001101------------0101----")
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//INST(thumb32_LDREXD, "LDREXD", "111010001101------------0111----")
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146
externals/dynarmic/src/frontend/A32/translate/impl/thumb32_load_store_dual.cpp
vendored
Executable file
146
externals/dynarmic/src/frontend/A32/translate/impl/thumb32_load_store_dual.cpp
vendored
Executable file
@ -0,0 +1,146 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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static bool ITBlockCheck(const A32::IREmitter& ir) {
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return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock();
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}
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static bool TableBranch(ThumbTranslatorVisitor& v, Reg n, Reg m, bool half) {
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if (m == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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if (ITBlockCheck(v.ir)) {
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return v.UnpredictableInstruction();
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}
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const auto reg_m = v.ir.GetRegister(m);
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const auto reg_n = v.ir.GetRegister(n);
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IR::U32 halfwords;
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if (half) {
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const auto data = v.ir.ReadMemory16(v.ir.Add(reg_n, v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(1))));
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halfwords = v.ir.ZeroExtendToWord(data);
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} else {
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halfwords = v.ir.ZeroExtendToWord(v.ir.ReadMemory8(v.ir.Add(reg_n, reg_m)));
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}
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const auto current_pc = v.ir.Imm32(v.ir.PC());
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const auto branch_value = v.ir.Add(current_pc, v.ir.Add(halfwords, halfwords));
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v.ir.UpdateUpperLocationDescriptor();
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v.ir.BranchWritePC(branch_value);
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v.ir.SetTerm(IR::Term::FastDispatchHint{});
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return false;
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}
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static bool LoadDualImmediate(ThumbTranslatorVisitor& v, bool P, bool U, bool W,
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Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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}
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return v.UnpredictableInstruction();
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}
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const u32 imm = imm8.ZeroExtend() << 2;
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm));
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const IR::U32 address_1 = P ? offset_address
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: reg_n;
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const IR::U32 address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.SetRegister(t, v.ir.ReadMemory32(address_1));
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v.ir.SetRegister(t2, v.ir.ReadMemory32(address_2));
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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static bool LoadDualLiteral(ThumbTranslatorVisitor& v, bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return v.UnpredictableInstruction();
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}
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if (W) {
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return v.UnpredictableInstruction();
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}
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const auto imm = imm8.ZeroExtend() << 2;
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const auto address_1 = U ? v.ir.Add(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm))
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: v.ir.Sub(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm));
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const auto address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.SetRegister(t, v.ir.ReadMemory32(address_1));
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v.ir.SetRegister(t2, v.ir.ReadMemory32(address_2));
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return true;
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}
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static bool StoreDual(ThumbTranslatorVisitor& v, bool P, bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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}
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if (n == Reg::PC || t == Reg::PC || t2 == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const u32 imm = imm8.ZeroExtend() << 2;
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 reg_t = v.ir.GetRegister(t);
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const IR::U32 reg_t2 = v.ir.GetRegister(t2);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm));
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const IR::U32 address_1 = P ? offset_address
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: reg_n;
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const IR::U32 address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.WriteMemory32(address_1, reg_t);
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v.ir.WriteMemory32(address_2, reg_t2);
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualImmediate(*this, false, U, true, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualImmediate(*this, true, U, W, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, true, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, W, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, false, U, true, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, true, U, W, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_TBB(Reg n, Reg m) {
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return TableBranch(*this, n, m, false);
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}
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bool ThumbTranslatorVisitor::thumb32_TBH(Reg n, Reg m) {
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return TableBranch(*this, n, m, true);
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}
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} // namespace Dynarmic::A32
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@ -179,6 +179,16 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_STMIA(bool W, Reg n, Imm<15> reg_list);
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bool thumb32_STMDB(bool W, Reg n, Imm<15> reg_list);
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// thumb32 load/store dual, load/store exclusive, table branch instructions
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bool thumb32_LDRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_TBB(Reg n, Reg m);
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bool thumb32_TBH(Reg n, Reg m);
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// thumb32 data processing (shifted register) instructions
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bool thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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