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https://github.com/pineappleEA/pineapple-src.git
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89 lines
3.0 KiB
ArmAsm
89 lines
3.0 KiB
ArmAsm
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/*
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* ARM NEON optimised Format Conversion Utils
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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* Copyright (c) 2015 Janne Grunau <janne-libav@jannau.net>b
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/arm/asm.S"
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function ff_int32_to_float_fmul_scalar_neon, export=1
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VFP vdup.32 q0, d0[0]
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VFP len .req r2
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NOVFP vdup.32 q0, r2
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NOVFP len .req r3
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vld1.32 {q1},[r1,:128]!
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vcvt.f32.s32 q3, q1
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vld1.32 {q2},[r1,:128]!
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vcvt.f32.s32 q8, q2
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1: subs len, len, #8
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pld [r1, #16]
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vmul.f32 q9, q3, q0
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vmul.f32 q10, q8, q0
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beq 2f
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vld1.32 {q1},[r1,:128]!
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vcvt.f32.s32 q3, q1
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vld1.32 {q2},[r1,:128]!
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vcvt.f32.s32 q8, q2
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vst1.32 {q9}, [r0,:128]!
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vst1.32 {q10},[r0,:128]!
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b 1b
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2: vst1.32 {q9}, [r0,:128]!
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vst1.32 {q10},[r0,:128]!
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bx lr
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.unreq len
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endfunc
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function ff_int32_to_float_fmul_array8_neon, export=1
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ldr r0, [sp]
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lsr r0, r0, #3
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subs r0, r0, #1
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beq 1f
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2:
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vld1.32 {q0-q1}, [r2,:128]!
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vld1.32 {q2-q3}, [r2,:128]!
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vld1.32 {d20}, [r3]!
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subs r0, r0, #2
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vcvt.f32.s32 q0, q0
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vcvt.f32.s32 q1, q1
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vdup.32 q8, d20[0]
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vcvt.f32.s32 q2, q2
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vcvt.f32.s32 q3, q3
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vmul.f32 q0, q0, q8
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vdup.32 q9, d20[1]
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vmul.f32 q1, q1, q8
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vmul.f32 q2, q2, q9
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vmul.f32 q3, q3, q9
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vst1.32 {q0-q1}, [r1,:128]!
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vst1.32 {q2-q3}, [r1,:128]!
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bgt 2b
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it lt
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bxlt lr
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1:
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vld1.32 {q0-q1}, [r2,:128]
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vld1.32 {d16[],d17[]}, [r3]
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vcvt.f32.s32 q0, q0
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vcvt.f32.s32 q1, q1
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vmul.f32 q0, q0, q8
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vmul.f32 q1, q1, q8
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vst1.32 {q0-q1}, [r1,:128]
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bx lr
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endfunc
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