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91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
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/* $OpenBSD: x86_arch.h,v 1.1 2016/11/04 17:30:30 miod Exp $ */
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/*
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* Copyright (c) 2016 Miodrag Vallat.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* The knowledge of the layout of OPENSSL_ia32cap_P is internal to libcrypto
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* (and, to some extent, to libssl), and may change in the future without
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* notice.
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*/
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/*
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* OPENSSL_ia32cap_P is computed at runtime by OPENSSL_ia32_cpuid().
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*
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* On processors which lack the cpuid instruction, the value is always
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* zero (this only matters on 32-bit processors, of course).
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*
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* On processors which support the cpuid instruction, after running
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* "cpuid 1", the value of %edx is written to the low word of OPENSSL_ia32cap_P,
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* and the value of %ecx is written to its high word.
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*
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* Further processing is done to set or clear specific bits, depending
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* upon the exact processor type.
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*
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* Assembly routines usually address OPENSSL_ia32cap_P as two 32-bit words,
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* hence two sets of bit numbers and masks. OPENSSL_cpu_caps() returns the
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* complete 64-bit word.
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*/
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/* bit numbers for the low word */
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#define IA32CAP_BIT0_FPU 0
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#define IA32CAP_BIT0_MMX 23
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#define IA32CAP_BIT0_FXSR 24
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#define IA32CAP_BIT0_SSE 25
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#define IA32CAP_BIT0_SSE2 26
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#define IA32CAP_BIT0_HT 28
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/* the following bits are not obtained from cpuid */
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#define IA32CAP_BIT0_INTELP4 20
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#define IA32CAP_BIT0_INTEL 30
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/* bit numbers for the high word */
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#define IA32CAP_BIT1_PCLMUL 1
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#define IA32CAP_BIT1_SSSE3 9
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#define IA32CAP_BIT1_FMA3 12
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#define IA32CAP_BIT1_AESNI 25
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#define IA32CAP_BIT1_OSXSAVE 27
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#define IA32CAP_BIT1_AVX 28
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#define IA32CAP_BIT1_AMD_XOP 11
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/* bit masks for the low word */
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#define IA32CAP_MASK0_MMX (1 << IA32CAP_BIT0_MMX)
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#define IA32CAP_MASK0_FXSR (1 << IA32CAP_BIT0_FXSR)
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#define IA32CAP_MASK0_SSE (1 << IA32CAP_BIT0_SSE)
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#define IA32CAP_MASK0_SSE2 (1 << IA32CAP_BIT0_SSE2)
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#define IA32CAP_MASK0_HT (1 << IA32CAP_BIT0_HT)
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#define IA32CAP_MASK0_INTELP4 (1 << IA32CAP_BIT0_INTELP4)
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#define IA32CAP_MASK0_INTEL (1 << IA32CAP_BIT0_INTEL)
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/* bit masks for the high word */
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#define IA32CAP_MASK1_PCLMUL (1 << IA32CAP_BIT1_PCLMUL)
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#define IA32CAP_MASK1_SSSE3 (1 << IA32CAP_BIT1_SSSE3)
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#define IA32CAP_MASK1_FMA3 (1 << IA32CAP_BIT1_FMA3)
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#define IA32CAP_MASK1_AESNI (1 << IA32CAP_BIT1_AESNI)
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#define IA32CAP_MASK1_AVX (1 << IA32CAP_BIT1_AVX)
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#define IA32CAP_MASK1_AMD_XOP (1 << IA32CAP_BIT1_AMD_XOP)
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/* bit masks for OPENSSL_cpu_caps() */
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#define CPUCAP_MASK_MMX IA32CAP_MASK0_MMX
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#define CPUCAP_MASK_FXSR IA32CAP_MASK0_FXSR
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#define CPUCAP_MASK_SSE IA32CAP_MASK0_SSE
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#define CPUCAP_MASK_INTELP4 IA32CAP_MASK0_INTELP4
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#define CPUCAP_MASK_PCLMUL (1ULL << (32 + IA32CAP_BIT1_PCLMUL))
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#define CPUCAP_MASK_SSSE3 (1ULL << (32 + IA32CAP_BIT1_SSSE3))
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#define CPUCAP_MASK_AESNI (1ULL << (32 + IA32CAP_BIT1_AESNI))
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