mirror of
https://github.com/pineappleEA/pineapple-src.git
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234 lines
7.3 KiB
ArmAsm
234 lines
7.3 KiB
ArmAsm
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/*
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* Copyright (c) 2014 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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#include "asm-offsets.h"
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.macro resample_one fmt, es=2
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.ifnc \fmt, dbl
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.macro M_MUL2 x:vararg
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.endm
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.macro M_MLA2 x:vararg
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.endm
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.endif
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function ff_resample_one_\fmt\()_neon, export=1
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sxtw x2, w2
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ldr x9, [x0, #FILTER_BANK]
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ldr w6, [x0, #FILTER_LENGTH]
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ldp w7, w8, [x0, #PHASE_SHIFT] // and phase_mask
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lsr x10, x4, x7 // sample_index
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and x4, x4, x8
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lsl x11, x6, #\es // filter_length * elem_size
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add x3, x3, x10, lsl #\es // src[sample_index]
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madd x9, x11, x4, x9 // filter
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cmp w6, #16
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b.lt 5f
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8: // remaining filter_length at least 16
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subs w6, w6, #16
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LOAD8 v4, v5, v6, v7, x3
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LOAD8 v16, v17, v18, v19, x9
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M_MUL v0, v4, v16, v1
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M_MUL2 v1, v6, v18
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7:
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LOAD8 v20, v21, v22, v23, x3
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M_MLA v0, v5, v17, v1
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M_MLA2 v1, v7, v19
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LOAD8 v24, v25, v26, v27, x9
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M_MLA v0, v20, v24, v1
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M_MLA2 v1, v22, v26
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b.eq 6f
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cmp w6, #16
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M_MLA v0, v21, v25, v1
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M_MLA2 v1, v23, v27
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b.lt 4f
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subs w6, w6, #16
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LOAD8 v4, v5, v6, v7, x3
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LOAD8 v16, v17, v18, v19, x9
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M_MLA v0, v4, v16, v1
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M_MLA2 v1, v6, v18
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b 7b
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6:
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M_MLA v0, v21, v25, v1
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M_MLA2 v1, v23, v27
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STORE_ONE 0, x1, x2, v1
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ret
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5:
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movi v0.16b, #0
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movi v1.16b, #0
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4: // remaining filter_length 1-15
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cmp w6, #4
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b.lt 2f
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subs w6, w6, #4
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LOAD4 v4, v5, x3
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LOAD4 v6, v7, x9
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M_MLA v0, v4, v6, v1
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M_MLA2 v1, v5, v7
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b.eq 0f
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b 4b
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2: // remaining filter_length 1-3
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cmp w6, #2
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b.lt 1f
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LOAD2 2, x3
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LOAD2 3, x9
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subs w6, w6, #2
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M_MLA v0, v2, v3
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b.eq 0f
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1: // remaining filter_length 1
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LOAD1 6, x3
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LOAD1 7, x9
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M_MLA v0, v6, v7
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0:
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STORE_ONE 0, x1, x2, v1
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ret
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endfunc
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.purgem LOAD1
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.purgem LOAD2
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.purgem LOAD4
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.purgem LOAD8
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.purgem M_MLA
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.purgem M_MLA2
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.purgem M_MUL
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.purgem M_MUL2
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.purgem STORE_ONE
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.endm
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.macro LOAD1 d1, addr
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ldr d\d1, [\addr], #8
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.endm
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.macro LOAD2 d1, addr
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ld1 {v\d1\().2d}, [\addr], #16
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.endm
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.macro LOAD4 d1, d2, addr
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ld1 {\d1\().2d,\d2\().2d}, [\addr], #32
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.endm
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.macro LOAD8 d1, d2, d3, d4, addr
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ld1 {\d1\().2d,\d2\().2d,\d3\().2d,\d4\().2d}, [\addr], #64
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.endm
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.macro M_MLA d, r0, r1, d2:vararg
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fmla \d\().2d, \r0\().2d, \r1\().2d
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.endm
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.macro M_MLA2 second:vararg
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M_MLA \second
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.endm
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.macro M_MUL d, r0, r1, d2:vararg
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fmul \d\().2d, \r0\().2d, \r1\().2d
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.endm
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.macro M_MUL2 second:vararg
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M_MUL \second
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.endm
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.macro STORE_ONE rn, addr, idx, d2
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fadd v\rn\().2d, v\rn\().2d, \d2\().2d
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faddp d\rn\(), v\rn\().2d
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str d\rn\(), [\addr, \idx, lsl #3]
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.endm
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resample_one dbl, 3
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.macro LOAD1 d1, addr
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ldr s\d1, [\addr], #4
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.endm
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.macro LOAD2 d1, addr
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ld1 {v\d1\().2s}, [\addr], #8
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.endm
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.macro LOAD4 d1, d2, addr
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ld1 {\d1\().4s}, [\addr], #16
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.endm
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.macro LOAD8 d1, d2, d3, d4, addr
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ld1 {\d1\().4s,\d2\().4s}, [\addr], #32
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.endm
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.macro M_MLA d, r0, r1, d2:vararg
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fmla \d\().4s, \r0\().4s, \r1\().4s
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.endm
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.macro M_MUL d, r0, r1, d2:vararg
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fmul \d\().4s, \r0\().4s, \r1\().4s
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.endm
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.macro STORE_ONE rn, addr, idx, d2
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faddp v\rn\().4s, v\rn\().4s, v\rn\().4s
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faddp s\rn\(), v\rn\().2s
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str s\rn\(), [\addr, \idx, lsl #2]
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.endm
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resample_one flt
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.macro LOAD1 d1, addr
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ldr h\d1, [\addr], #2
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.endm
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.macro LOAD2 d1, addr
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ldr s\d1, [\addr], #4
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.endm
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.macro LOAD4 d1, d2, addr
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ld1 {\d1\().4h}, [\addr], #8
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.endm
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.macro LOAD8 d1, d2, d3, d4, addr
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ld1 {\d1\().4h,\d2\().4h}, [\addr], #16
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.endm
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.macro M_MLA d, r0, r1, d2:vararg
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smlal \d\().4s, \r0\().4h, \r1\().4h
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.endm
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.macro M_MUL d, r0, r1, d2:vararg
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smull \d\().4s, \r0\().4h, \r1\().4h
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.endm
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.macro STORE_ONE rn, addr, idx, d2
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addp v\rn\().4s, v\rn\().4s, v\rn\().4s
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addp v\rn\().4s, v\rn\().4s, v\rn\().4s
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sqrshrn v\rn\().4h, v\rn\().4s, #15
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str h\rn\(), [\addr, \idx, lsl #1]
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.endm
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resample_one s16, 1
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.macro LOAD1 d1, addr
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ldr s\d1, [\addr], #4
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.endm
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.macro LOAD2 d1, addr
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ld1 {v\d1\().2s}, [\addr], #8
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.endm
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.macro LOAD4 d1, d2, addr
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ld1 {\d1\().4s}, [\addr], #16
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.endm
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.macro LOAD8 d1, d2, d3, d4, addr
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ld1 {\d1\().4s,\d2\().4s}, [\addr], #32
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.endm
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.macro M_MLA d1, r0, r1, d2:vararg
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smlal \d1\().2d, \r0\().2s, \r1\().2s
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.ifnb \d2
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smlal2 \d2\().2d, \r0\().4s, \r1\().4s
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.endif
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.endm
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.macro M_MUL d1, r0, r1, d2:vararg
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smull \d1\().2d, \r0\().2s, \r1\().2s
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.ifnb \d2
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smull2 \d2\().2d, \r0\().4s, \r1\().4s
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.endif
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.endm
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.macro STORE_ONE rn, addr, idx, d2
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add v\rn\().2d, v\rn\().2d, \d2\().2d
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addp d\rn\(), v\rn\().2d
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sqrshrn v\rn\().2s, v\rn\().2d, #30
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str s\rn\(), [\addr, \idx, lsl #2]
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.endm
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resample_one s32
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